Various kinds of conductive materials are used in semiconductor devices. The conductive materials may form an interconnection structure that connects electrical components in the semiconductor devices. A metallic process for forming an interconnection structure is typically a finishing step in forming integrated circuit devices and may affect the yield and/or reliability of such devices.
The conductive materials may make contact with different conductive materials and insulating materials. As a result, the conductive material may be pilled off due to differences in thermal expansion coefficients. In addition, when different conductive materials contact each other, a low-conductivity material may be formed, which may raise the resistance of an interconnection structure. To solve those problems, a specific conductive material referred to as “a barrier metal layer” has been used.
A barrier metal layer is conventionally used in connecting different conductive patterns through a gap region having a relatively large aspect ratio, such as a contact hole or a via hole. It is generally desirable that the barrier metal layer have good step coverage to conformally cover a gap region that has a relatively large aspect ratio. As mentioned above, the barrier metal layer may be formed in a final processing step; that is, it may be formed on a resultant structure with a transistor or a capacitor or the like. The step of forming the barrier metal layer may be, therefore, performed at a relatively low temperature to avoid damaging the transistor and/or the capacitor due to a high temperature. It may also be desirable to form the barrier metal layer at a relatively low temperature when the interconnection structure includes an aluminum layer that has a relatively low melting point.
The barrier metal layer may be formed by means of physical vapor deposition (PVD), for example, a sputtering method. Unfortunately, PVD typically provides relatively poor step coverage making PVD less desirable for use in forming a barrier metal layer in a gap region that has a relatively large aspect ratio.
A method of forming a barrier metal layer by using chemical vapor deposition (CVD) has been proposed to solve the problem caused by PVD. The CVD method can be used to form a barrier metal layer that has relatively good step coverage, but, unfortunately, raises the process temperature. A metal organic CVD method has been used, however, which provides a relatively low temperature process and relatively good step coverage.
FIGS. 1 and 2 are cross-sectional views that illustrate a conventional method of forming a conductive structure on a semiconductor substrate. Referring now to FIGS. 1 and 2, a lower conductive pattern 20 is formed on a semiconductor substrate 10. An interlayer dielectric layer 30 is formed on a surface of the semiconductor substrate 10 with the lower conductive pattern 20, and then patterned to form a via hole 35 that exposes a top surface of the lower conductive pattern 20. A barrier metal layer 40 is formed to conformally cover an inner sidewall of the via hole 35 and a top surface of the interlayer dielectric layer 30. The barrier metal layer 40 is formed by using CVD with a metal organic precursor. An upper conductive layer 50 is then formed on the barrier metal layer 40 to fill the via hole 35.
Carbon may be included in the barrier metal layer 40 because of the metal organic precursor. In this case, the barrier metal layer 40 may have a relatively porous structure. When the porous barrier metal layer 40 is exposed in a fabrication line, oxygen in the air may penetrate the barrier metal layer 40. The penetration of oxygen may increase the resistance of the barrier metal layer 40, which may result in signal transfer delay and/or power dissipation. A plasma treatment may be applied during or immediately after forming the barrier metal layer 40. The plasma treatment may reduce or remove the carbon in the barrier metal layer 40 that was formed due to use of the metal organic precursor.
According to an experiment performed using the conventional method described above with respect to FIGS. 1 and 2, the gap fill characteristic of the upper conductive layer 50 was generally good if the aspect ratio (h1/W1) of the via hole 35 is four or less as illustrated in FIG. 1. When the aspect ratio (h2/W2) of the via hole 35 was increased, however, the upper conductive layer 50 could not fill the via hole 35 completely as illustrated in FIG. 2.
The plasma treatment may be less effective as the aspect ratio increases because of the relation between the aspect ratio and the gap fill characteristic. That is, it may be difficult for ionized atoms to reach a lower part of the gap region that has a large aspect ratio, such that the carbon may not be effectively removed there. Thus, the oxygen penetrating the region, including non-removed carbon, is outgassed before a subsequent upper metal layer 50 is formed. The outgassed gas may degrade the gap fill characteristic and the adhesion characteristic of the upper metal layer 50. As a result, voids 55 may be formed in the via hole, as shown in FIG. 2.